Speaker: Sachin S. Sapatnekar, University of Minnesota, Minneapolis, MN, USA

 

Abstract:

As CMOS technologies have shrunk to the scale of tens of nanometers, aging problems have emerged as a major challenge. There has been tremendous progress in developing new methods for modeling and diagnosing reliability at the level of individual transistors, but much less work on propagating these models to higher levels of abstraction to predict the reliability of larger circuits. This talk will discuss techniques used to estimate and enhance the reliability of large digital circuits, so that they live and age well. Specific solutions that could practically be applied to analyze or improve the lifetime of a design, under phenomena such as bias temperature instability, gate oxide breakdown, and electromigration, will be exemplified. In fact, it will be demonstrated that circuits have "immune systems" that make them inherently resilient to some failure modes, and we will explore how immunity can be boosted through presilicon and postsilicon optimization.

 

Biography:

The speaker received his Ph.D. from the University of Illinois at Urbana-Champaign in 1992. He is currently at the University of Minnesota, where he holds the Distinguished McKnight University Professorship and the Henle Professorship in ECE. His research is related to developing CAD techniques for the analysis and optimization of circuit performance. He served as General Chair for the 2010 ACM/IEEE Design Automation Conference (DAC) and is currently Editor-in-Chief of the IEEE Transactions on CAD. He has received several conference Best Paper awards, and the SRC Technical Excellence award, and is an IEEE fellow.