Dr. Joungho Kim received B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1984 and 1986, respectively, and Ph.D degree in electrical engineering from the University of Michigan, Ann Arbor, in 1993. In 1994, he joined Memory Division of Samsung Electronics, where he was engaged in Gbit-scale DRAM design.

In 1996, he moved to KAIST (Korea Advanced Institute of Science and Technology). He is currently a Professor at Electrical Engineering and Computer Science Department, and the group director of Convergence Device and System Group. Since joining KAIST, his research centers on EMC modeling, design, and measurement methodologies of 3D IC, System-in-Package(SiP), and multi-layer PCB. Especially, his major research topic is focused on chip-package co-design and simulation for signal integrity, power integrity, ground integrity, timing integrity, and radiated emission of 3D IC and SiP. He has successfully demonstrated low noise and high performance designs of numerous SiP’s for wireless communication applications such as ZigBee, T-DMB, NFC, and UWB. He was on a sabbatical leave during an academic year from 2001 to 2002 at Silicon Image Inc., Sunnyvale CA. He was responsible for low noise package designs for SATA, FC, HDMI, and Panel Link SerDes devices.

He has authored and co-authored over 280 technical papers published at refereed journals and conference proceedings in modeling, design, and measurement of 3D IC, SiP, and PCB. Also, he has given more than 130 invited talks and tutorials at the academia and the related industries. He received Outstanding Academic Achievement Faculty Award of KAIST in 2006, and Best Faculty Research Award of KAIST in 2008. Dr. Joungho Kim was the symposium chair of IEEE EDAPS 2008 Symposium. He is appointed as an IEEE EMC society distinguished lecturer in a period from 2009-2011. Currently, he is an associated editor of the IEEE Transactions of Electromagnetic Compatibility, and is serving as a guest editor of the special issue in the IEEE Transactions of Electromagnetic Compatibility for PCB level signal integrity, power integrity, and EMI/EMC.

 IEEE EMC Society Distinguished Lecture

Title: Signal Integrity of TSV Based 3D IC

Abstract:

Recently, process dimensions of Silicon based semiconductor devices are reaching less than 20 nm scale. However, it suffers significant technical and business challenges including enlarged leakage current and considerable increase of investment budget. As a result, new TSV (Through Silicon Via) based 3D IC technology is emerging as a promising next generation IC technology in both semiconductor industry and academia. In the 3D IC, very thin semiconductor dies of less than 30 um are vertical stacked to minimize the package size and to maximize the semiconductor system performances. In the 3D IC, TSV is becoming the most critical vertical interconnection structure between the semiconductor dies. Around world, most of the semiconductor companies including Intel, IBM, TI, AMD and Qualcomm are seriously considering the TSV based 3D IC as a future direction of the semiconductor integration technology.

In the TSV based 3D IC, signal integrity is becoming the major design obstacle due to the high frequency loss, coupling, and electromagnetic radiation, while more than thousand of vertical and lateral interconnections are routed in a tiny 3D space. It could be even more serious in 3D IC for the applications of high-density and multi-function mobile multimedia, computing, and communication system platforms. In this talk, new modeling, measurement, design, and analysis approaches will be introduced in order to enhance the performance and reliability of the 3D IC.

Outline:

1.      Introduction:

2.      Market and technical trend of 3D IC

3.      TSV Models

4.      High frequency loss and equalizer design

5.      TSV noise couplings and shielding methods: TSV to TSV and TSV to active

6.      Die to Die Vertical coupling

7.      PDN design issues in TSV based 3D IC

8.      Conclusions.